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d igital audio driver with discrete deadtime and protection product summary v supply 200 v max. i o +/- 1 a / 1.2 a typ. selectable deadtime 15 ns, 25 ns, 35 ns, 45 ns typ. prop delay time 60 ns typ. bi-directional over- current sensing package typical application diagram irs20124(s)pbf data sheet no. pd60240 www.irf.com 1 14-lead soic features ? 200 v high voltage ratings deliver up to 1000 w output power in class d audio amplifier applications ? integrated deadtime generation and bi-directional over-current sensing simplify design ? programmable compensated preset deadtime for improved thd performances over temperature ? high noise immunity ? shutdown function protects devices from overload conditions ? operates up to 1 mhz ? 3.3 v/5 v logic compatible input <200 v ho nc vs ocset 1 oc v cc sd dt/sd com ocset 2 in vb lo irs20124 nc nc <20 v <20v in oc ? rohs compliant
www.irf.com 2 irs20124s (pbf) symbol definition min. max. units v b high-side floating supply voltage -0.3 220 v s high-side floating supply voltage v b -20 v b +0.3 v ho high-side floating output voltage vs-0.3 v b +0.3 v cc low-side fixed supply voltage -0.3 20 v lo low-side output voltage -0.3 vcc+0.3 v in input voltage -0.3 vcc+0.3 v oc oc pin input voltage -0.3 vcc+0.3 v ocset1 ocset1 pin input voltage -0.3 vcc+0.3 v ocset2 ocset2 pin input voltage -0.3 vcc+0.3 dvs/dt allowable vs voltage slew rate - 50 v/ns p d maximum power dissipation - 1.25 w rth ja thermal resistance, junction to ambient - 100 c/w t j junction temperature - 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) - 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. all currents are defined positive into any lead. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. description the irs20124 is a high voltage, high speed power mosfet driver with internal deadtime and shutdown functions specially designed for class d audio amplifier applications. the internal dead time generation block provides accurate gate switch timing and enables tight deadtime settings for better thd performances. in order to maximize other audio performance characteristics, all switching times are designed for immunity from external disturbances such as v cc perturbation and incoming switching noise on the dt pin. logic inputs are compatible with lsttl output or standard cmos down to 3.0 v without speed degradation. the output drivers feature high current buffers capable of sourcing 1.0 a and sinking 1.2 a. internal delays are optimized to achieve minimal deadtime variations. proprietary hvic and latch immune cmos technologies guarantee operation down to v s = ?4 v, providing outstanding capabilities of latch and surge immunities with rugged monolithic construction. v c
www.irf.com3 irs20124s (pbf) note 1: logic operational for v s equal to -8 v to 200 v. logic state held for v s equal to -8 v to -v bs . recommended operating conditions for proper operation, the device should be used within the recommended conditions. the vs and com offset ratings are tested with all supplies biased at a 15 v differential. symbol definition min. max. units v b high-side floating supply absolute voltage vs+10 vs+18 v s high-side floating supply offset voltage note 1 200 v ho high-side floating output voltage v s v b v cc low-side fixed supply voltage 10 18 v lo low-side output voltage 0 v cc v in logic input voltage 0 v cc v oc oc pin input voltage 0 v cc v ocset1 ocset1 pin input voltage 0 v cc v ocset2 ocset2 pin input voltage 0 v cc t a ambient temperature -40 125 c dynamic electrical characteristics v bias (v cc , v bs ) = 15 v, c l = 1n f and t a = 25 c unless otherwise specified. fig. 2 shows the timing definitions. symbol definition min. typ. max. units t est conditions t on high & low-side turn-on propagation delay ? 60 80 v s =0 v t off high & low-side turn-off propagation delay ? 60 80 v s =200 v t r turn-on rise time ? 25 40 t f turn-off fall time ? 15 35 t sd shutdown propagation delay ? 140 200 t oc propagation delay time from v s >v soc + to oc ? 280 ? oc set1 =3.22 v oc set2 =1.20 v t woc min oc pulse width ? 1 0 0 ? t oc filt oc input filter time ? 200 ? dt1 deadtime: lo turn-off to ho turn-on (dt lo-ho ) & ho turn-off to lo turn-on (dt ho-lo ) 01540 v dt >v dt1 dt2 deadtime: lo turn-off to ho turn-on (dt lo-ho ) & ho turn-off to lo turn-on (dt ho-lo ) 5 v dt1 >v dt > v dt2 dt3 deadtime: lo turn-off to ho turn-on (dt lo-ho ) & ho turn-off to lo turn-on (dt ho-lo ) dt4 deadtime: lo turn-off to ho turn-on (dt lo-ho ) & ho turn-off to lo turn-on (dt ho-lo )v d t= v dt4 ns v 5 25 50 10 35 60 15 45 70 v dt3 >v dt >v dt4 v dt2 >v dt >v dt3
www.irf.com 4 irs20124s (pbf) static electrical characteristics v bias (v cc , v bs ) = 15 v and t a = 25 c unless otherwise specified. symbol definition min. typ. max. units t est conditions v ih logic high input voltage 2.5 ? ? vcc=10 v -20 v v il logic low input voltage ? ? 1.2 v oh high level output voltage, v bias ? v o ? ? 1.2 v ol low level output voltage, v o ? ? 0.1 uv cc+ v cc supply uvlo positive threshold 8.3 9.0 9.7 uv cc- v cc supply uvlo negative threshold 7.5 8.2 8.9 uv bs+ high-side well uvlo positive threshold 8.3 9.0 9.7 uv bs- high-side well uvlo negative threshold 7.5 8.2 8.9 i qbs high-side quiescent current ? ? 1 i qcc low-side quiescent current ? ? 4 v dt =vcc i lk high-to-low-side leakage current ? ? 50 v b =v s =200 v i in+ logic ?1? input bias current ? 3 10 v in =3.3 v i in- logic ?0? input bias current ? 0 1.0 v in =0v i o+ output high short circuit current (source) ? 1.0 ? vo=0 v, pw<10 s i o- output low short circuit current (sink) ? 1.2 ? vo=15 v, pw<10 s v dt1 dt mode select threshold 1 0.8(vcc) 0.89(vcc) 0.97(vcc) v dt2 dt mode select threshold 2 0.51(vcc) 0.57(vcc) 0.63(vcc) v dt3 dt mode select threshold 3 0.32(vcc) 0.36(vcc) 0.40(vcc) v dt4 dt mode select threshold 4 0.21(vcc) 0.23(vcc) 0.25(vcc) v soc+ oc threshold in v s 0.75 1.0 1.25 oc set1 =3.22 v oc set2 =1.20 v v soc- oc threshold in v s -1.25 -1.0 -0.75 oc set1 =3.22 v oc set2 =1.20 v a ma v v a io=0 a
www.irf.com 5 irs20124s (pbf) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 in ocset1 dt/sd ocset2 oc com lo v cc nc vs ho vb nc nc ir20124s 14 lead soic (narrow body) lead definitions symbol description vcc low-side logic supply voltage vb high-side floating supply ho high-side output vs high-side floating supply return in logic input for high-side and low-side gate driver outputs (ho and lo), in phase with ho dt/sd input for programmable deadtime, referenced to com. shutdown lo and ho when tied to com com low-side supply return lo low-side output oc over-current output (negative logic) oc set1 input for setting negative over current threshold oc set2 input for setting positive over current threshold
www.irf.com 6 irs20124s (pbf) block diagram sd level shifter uv detect vb ho vs in dead time dt/sd uv q s r current sensing uv detect delay oc ocset1 o c s e t 2 vcc lo com
www.irf.com 7 irs20124s (pbf) dt/sd ho lo v sd t sd 90% figure 1. switching time waveform definitions figure 2. shutdown waveform definitions 50% 50% t off(l) t on(l) 90% 10% 90% 10% dt ho-lo t off(h) in ho lo t on(h) dt lo-ho
www.irf.com 8 irs20124s (pbf) figure 4. oc waveform definitions toc filt high vs oc v soct com com twoc vs oc v soc+ tdoc com com lo v soc- in ocset1 dt/sd ocset2 oc com lo v cc nc vs ho vb nc nc __ 15v 15v vsoc+ vsoc- 10k oc vsoc+ vsoc- com vs oc figure 5. oc waveform definitions figure 3. oc input filtertime definitions
www.irf.com9 irs20124s (pbf) 0 40 80 120 160 200 -50 -25 0 25 50 75 100 125 temperature ( o c) figure 6a. turn-on time vs . te m pe rature 0 40 80 120 160 200 10 12 14 16 18 20 v bias supply voltage (v) figure 6b. turn-on time vs . supply voltage turn-on delay time (ns) turn-on delay time (ns) ty p. ma x . 0 30 60 90 120 150 10 12 14 16 18 20 v bias supply voltage (v) figure 7b. turn-off time vs. supply voltage turn-off time (ns) ty p. ma x . 0 0 0 0 0 0 -50 -25 0 25 50 75 100 125 temperature ( o c) 0 30 60 90 120 150 turn-off time (ns) figure 7a. turn-off time vs. temperature
www.irf.com 10 irs20124s (pbf) 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on rise time (ns) fiure 8a. turn-on rise tim e vs.tem perature 10 20 30 40 50 60 10 12 14 16 18 20 v bias supply voltage (v) turn-on rise time (ns) figure 8b. turn-on rise time vs . supply voltage 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off fall time (ns) figure 9a. turn-off fall tim e vs. tem perature 0 10 20 30 40 50 10 12 14 16 18 20 v bias supply voltage (v) turn-off fall time (ns) figure 9b. turn-off fall tim e vs . supply voltage
www.irf.com 11 irs20124s (pbf) min . 1 2 3 4 5 10 12 14 16 18 20 v cc supply voltage (v) input voltage (v) figure 10b. logic "1" input voltage vs. supply voltage max . 0 1 2 3 4 -50-250 255075100125 temperatre ( o c) input voltage (v) figure 11a. logic "0" input voltage vs. temperature max. 0 1 2 3 4 10 12 14 16 18 20 v cc supply voltage (v) input voltage (v) figure 11b. logic "0" input voltage vs. su pp l y volta g e min . 1 2 3 4 5 -50-250 255075100125 temperature ( o c) input voltage (v) figure 10a. logic "1" input voltage vs. tem perature
www.irf.com 12 irs20124s (pbf) max . -1 0 1 2 3 4 -50-250 255075100125 temperature ( o c) high level output voltage (v) figure 12a. high level output vs. temperature max . 0.00 0.05 0.10 0.15 0.20 0.25 -50-250 255075100125 temperature ( o c) low level output voltage (v) figure 13a. low level output vs.temperature max . 0.00 0.05 0.10 0.15 0.20 0.25 10 12 14 16 18 20 v cc supply voltage (v) low level output voltage (v) figure 13b. low level output vs. supply voltage ma x . 0 1 2 3 4 10 12 14 16 18 20 v cc supply voltage (v) high level output voltage (v ) figure 12b. high level output vs. supply voltage
www.irf.com 13 irs20124s (pbf) max . 0 50 100 150 200 250 300 -50 -25 0 25 50 75 100 125 temperature ( o c) offset supply leakage current ( a) figure 14a. offset supply leakage current vs. temperature v b = 200 v ma x . typ. -10 10 30 50 70 90 110 50 80 110 140 170 200 v b boost voltage (v) offset supply leakage current ( a) figure 14b. offset supply leakage current vs. supply voltage 0.0 0.5 1.0 1.5 2.0 2.5 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs supply current ( m a ) figure 15a. v bs supply current vs . te m p erature 0 1 1 2 2 3 10 12 14 16 18 20 v bs supply voltage (v) v bs supply current ( m a ) figure 15b. v bs supply current vs . supply voltage
www.irf.com 14 irs20124s (pbf) max . 0 2 4 6 8 10 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc supply current ( a) figur e 16a. v cc supply current vs. temperature ma x . 0 2 4 6 8 10 10 12 14 16 18 20 v cc supply voltage (v) v cc supply current ( ? ) fi gu r e 16b. v cc supply curr ent vs. supply voltage 0 6 12 18 24 30 -50 -25 0 25 50 75 100 125 temperature ( o c) logic "1" input current ( m a ) figure 17a. logic "1" input current vs. tem perature 0 6 12 18 24 30 10 12 14 16 18 20 v cc supply v oltage (v ) logic "1" input current ( m a ) figure 17b. logic "1" input current vs. supply voltage
www.irf.com 15 irs20124s(pbf) typ. max. min. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v c c s u p p l y c u r r e n t (ma) figure 19. v cc undervoltage threshold (+) vs. temperature typ. max. min. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v c c s u p p l y c u r r e n t (m a ) figure 20. v cc undervoltage threshold (-) vs. temperature max 0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature (c) l o g i c " 0 " i n p u t b i a s c u r r e n t ( a ) max 0 1 2 3 4 5 6 10 12 14 16 18 20 supply voltage (v) l o g i c " 0 " i n p u t b i a s c u r r e n t ( a ) f i g u r e 1 8a. logic "0" input bias current v s . t e m p e r a t u re figure 18b. logic "0" input bias current vs. voltage
www.irf.com 16 irs20124s (pbf) typ. 0.5 0.7 0.9 1.1 1.3 1.5 10 12 14 16 18 20 v bias supply voltage (v) output source current ( ) figure 23. output source current vs. supply voltage ty p. 0.5 0.7 0.9 1.1 1.3 1.5 10 12 14 16 18 20 v bias supply voltage (v) output sink current ( ) figure 24. output sink current vs. supply voltage 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs supply current ( m a ) figure 21. v bs undervoltage threshold (+) vs. tem perature 6 7 8 9 10 11 -50-25 0 25 50 75100125 temperature ( o c) v bs supply current ( m a ) figure 22. v bs undervoltage threshold (-) vs. tem perature
www.irf.com 17 irs20124s (pbf) typ. -15 -13 -11 -9 -7 -5 10 12 14 16 18 20 v bs floting supply voltage (v) v s offset supply voltage (v) figure 25. maximum v s negative offset vs. supply voltage typ. max . min. 11 12 13 14 15 16 -50 -25 0 25 50 75 100 125 temperature ( o c) v dt1 (v) figure 26. dt mode select threshold (1) vs. temperature typ. max . min. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v dt2 (v) figure 27. dt mode select threshold (2) vs. temperature ty p. max . min. 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 temperature ( o c) v dt3 (v) figure 28. dt mode select threshold (3) vs. temperature
www.irf.com 18 irs20124s (pbf) typ. 20 28 36 44 52 60 -50 -25 0 25 50 75 100 125 temperature ( o c) dt lo-ho (ns) figure 30. dt lo turn-off to ho turnoon (3) vs. temperature 2.0 2.5 3.0 3.5 4.0 4.5 -50 -25 0 25 50 75 100 125 temperature ( o c) v dt4 (v) figure 29. dt mode select threshold (4) vs. tem perature ty p. ma x . min . -1.8 -1.5 -1.2 -0.9 -0.6 -0.3 -50-25 0 255075100125 temperature ( o c) negative oc th (v ) figure 32. negative oc threshold(-) in v s vs . te m p erature typ. ma x . min . 0.0 0.4 0.8 1.2 1.6 2.0 -50 -25 0 25 50 75 100 125 temperature ( o c) positive oc th (v) figure 31. positive oc threshold(+) in v s vs . te m p erature
www.irf.com 19 irs20124s(pbf) 14 0 v 70 v 0v 15 25 35 45 55 65 1 10 100 1000 frequency (khz) temperature ( o c) figure 32. irs20124s vs. frequency (irfbc20) r gate =33 ? , v cc =12 v 14 0 v 70 v 0v 15 25 35 45 55 65 1 10 100 1000 frequency (khz) temperature ( o c) figure 33. irs20124s vs. frequency (irfbc30) r gate =22 ? , v cc =12 v 14 0 v 70 v 0v 15 25 35 45 55 65 1 10 100 1000 frequency (khz) temperature ( o c) figure 34. irs2 0124s vs. frequency (irfbc40) r gate =15 ? , v cc =12 v 14 0 v 70 v 0v 15 25 35 45 55 65 75 1 10 100 1000 frequency (khz) temperature ( o c) figure 35. irs2 0124s vs. frequency (irfpe5 0) r gate =10 ? , v cc =12 v 33 . 34. 35. 36.
www.irf.com 20 irs20124s (pbf) functional description programmable dead-time the irs20124 has an internal deadtime genera tion block to reduce the number of external components in the output stage of a class d audio am plifier. selectable deadtime through the dt/sd pin volt- age is an easy and reliable function, which re- quires only two external resistors. the deadtime generation block is also designed to provide a constant deadtime interval, independent of v cc fluctuations. since the timings are critical to the audio performance of a class d audio amplifier, the unique internal deadtime generation block is designed to be immune to noise on the dt/sd pin and the vcc pin. noise-free programmable deadtime function is available by selecting deadtime from four preset values, which are opti- mized and compensated. how to determine optimal deadtime please note that the effective deadtime in an actual application differs from the deadtime specified in this datasheet due to finite fall time, t f . the deadtime value in this datasheet is defined as the time period from the starting point of turn-off on one side of the switching stage to the starting point of turn-on on the other side as shown in fig. 5. the fall time of mosfet gate voltage must be subtracted from the deadtime value in the datasheet to determine the effective dead time of a class d audio amplifier. (effective deadtime) = (deadtime in datasheet) ? (fall time, t f ) ho (or lo) lo (or ho) tf dead- time effective dead-time 10% 10% 90% effective deadtime a longer deadtime period is required for a mosfet with a larger gate charge value because of the longer t f . a shorter effective deadtime setting is always beneficial to achieve better linearity in the class d switching stage. however, the likelihood of shoot-through current increases with narrower deadtime settings in mass production. negative values of effective deadtime may cause excessive heat dissipation in the mosfets, potentially leading to their serious damage. to calculate the optimal deadtime in a given application, the fall time (t f )for both output voltages, ho and lo, in the actual circuit needs to be measured. in addition, the effective deadtime can also vary with temperature and device parameter variations. therefore, a minimum effective deadtime of 10 ns is recommended to avoid shoot-through current over the range of operating temperatures and supply voltages.
www.irf.com 21 irs20124s (pbf) dt/sd pin dt/sd pin provides two functions: 1) setting dead- time and 2) shutdown. the irs20124 determines its operation mode based on the voltage applied to the dt/sd pin. an internal comparator translates which mode is being used by comparing internal reference voltages. threshold voltages for each mode are set internally by a resistive voltage divider off v cc , negating the need of using a precise absolute voltage to set the mode. vcc 0.89xvcc 0.57xvcc 0.36xvcc 0.23xvcc shutdown 45ns 35ns 25ns 15ns operational mode v dt dead-time deadtime settings vs v dt voltage design example table 1 shows suggested values of resistance for setting the deadtime. resistors with up to 5% tolerance can be used if these listed values are followed. vcc com dt/sd >0.5ma r1 r2 irs20124 table 1. suggested resistor values for deadtime settings shutdown since irs20124 has internal deadtime generation, independent inputs for ho and lo are no longer provided. shutdown mode is the only way to turn off both mosfets simultaneously to protect them from over current conditions. if the dt/sd pin de- tects an input voltage below the threshold, v dt4, the irs20124 will output 0 v at both ho and lo outputs, forcing the switching output node to go into a high impedance state. over current sensing in order to protect the power mosfet, irs20124 has a feature to detect over-current conditions, which can occur when speaker wires are shorted together. the over-current shutdown feature can be configured by combining the current sensing function with the shutdown mode via the dt/sd pin. load current direction in class d audio application in a class d audio amplifier, the direction of the load current alternates according to the audio in- put signal. an over current condition can therefore happen during either a positive current cycle or a negative current cycle. it should be noted that external resistor deadtime mode r1 (?) r2 (?) dt/sd (v) dt1 <10k open 1.00 (vcc) dt2 3.3k 8.2k 0.71 (vcc) dt3 5.6k 4.7k 0.46 (vcc) dt4 8.2k 3.3k 0.29 (vcc)
www.irf.com 22 irs20124s (pbf) each mosfet carries a part of the load current in an audio cycle. bi-directional current sensing offers over current detection capabilities in both cases by monitoring only the low side mosfet. load current 0 bi-directional current sensing irs20124 has an over-current detection function utilizing r ds(on) of the low side switch as a current sensing shunt resistor. due to the proprietary hvic process, the irs20124 is able to sense nega tive as well as positive current flow, enabling bi-direc- tional load current sensing without the need for any additional external passive components. direction in mosfet current and load current v s vsoc+ vsoc- com ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ (a ) normal operation condition (b ) over- current in positive load current (c ) over- current in negative load current vs waveform in over-current condition irs20124 measures the current during the period when the low side mosfet is turned on. under normal operating conditions, v s voltage for the low side switch is well within the trip threshold bound- aries, v soc- and v soc+. in the case of fig. 9(b) which demonstrates the amplifier sourcing too much cur- rent to the load, the vs node is found below the trip level, v soc- . in fig. 9(c) with opposite current direc- tion, the amplifier sinks too much current from the load, positioning v s well above trip level, v soc+. once the voltage in v s exceeds the preset thresh- old, the oc pin pulls down to com to detect an over-current condition. since the switching waveform usually contains over/under shoot and associated oscillatory arti- facts on their transient edges, a 200 ns blanking interval is inserted in the v s voltage sensing block at the instant the low side switch is engaged. because of this blanking interval, the oc function will be unable to detect over current conditions if the low side on duration less than 200 ns. oc set1 oc set2 vs lo oc + + - - or and simplified functional block diagram of bi-directional current sensing the bi-directional current sensing block has an internal v level shifter feeding the signal to the comparator. oc set1 sets the threshold, and is given a trip level at v soc+ , which is oc set1 -v. in the same way, for a given oc set2 , v soc- is set at oc set2 -v.
www.irf.com 23 irs20124s (pbf) external resistor network to set oc threshold vcc com oc set1 >0.5ma r3 r4 r5 oc set2 how to set oc threshold the positive and negative trip thresholds for bi- directional current sensing are set by the voltages at oc set1 and oc set2 . the trip threshold voltages, v soc+ and v soc+, are determined by the required trip current levels, i trip+ i trip- , and r ds(on) in the low side mosfet. since the sensed voltage of v s is shifted up by 2.21 v internally and compared with the voltages fed to the oc set1 and oc set2 pins, the required value of oc set1 with respect to com is v ocset1 = v soc+ + 2.21 v = i x r ds(on) + 2.21 v the same relation holds between oc set2 and v soc-, v ocset2 = v soc- + 2.21 v = i x r ds(on) + 2.21 v in general, r ds(on) has a positive temperature co- efficient that needs to be considered when the threshold level is being set. please also note that, in the negative load current direction, the sensing voltage at the v s node is limited by the body di- ode of the low side mosfet as explained later. design example this example demonstrates how to use the ex ter- nal resistor network to set i trip+ and i trip- to be 11 a, using a mosfet that has r ds(on) =6 0 ?. v iset1 = v th + + 2.21 v = i trip+ x r ds(on) + 2.21 v = 11 x 60 ? +2.21 v = 2.87 v v iset2 = v th- + 2.21 v = i trip- x r ds(on) + 2.21 v = (?11) v 60 ? +2.21 v = 1.55 v the total resistance of resistor network is based on the voltage at the v cc and required bias cur- rent in this resistor network. r total =r3 + r4 + r5 = vcc / i bias = 12 v / 1 ? = 12 k ? the expected voltage across r3 is vcc- v iset1 = 12 v - 2.87 v=9.13 v. similarly, the voltages across r4 is v soc+ - v soc- = 2.87 v - 1.55 v =1.32 v, and the voltage across r5 is v iset2 = 1.55 v respectively. r3 =9.13 v/ i bias = 9.13 k? r4 =1.32 v/ i bias = 1.32 k? r5 =1.55 v/ i bias = 1.55 k? choose r3= 9.09 k w r4=1.33 kw, r5=1.54 k w from e-96 series. consequently, actual threshold levels are v soc+ =2.88 v gives i trip+ = 11.2 a v soc- =1.55 v gives i trip- = -11.0 a resisters with 1% tolerances are recommended.
www.irf.com 24 irs20124s (pbf) oc output signal the oc pin is a 20 v open drain output. the oc pin is pulled down to ground when an over current condition is detected. a single external pull-up resistor can be shared by multiple irs20124 oc pins to form the oring logic. in order for a micro- processor to read the oc signal, this information is buffered with a mono stable multi vibrator to ensure 100 ns minimum pulse width. because of unpredictable logic status of the oc pin, the oc signal should be ignored during power up/down. limitation from body diode in mosfet when a class d stage outputs a positive current, flowing from the class d amp to the load, the body diode of the mosfet will turn on when the drain to source voltage of the mosfet become larger than the diode forward drop voltage. in such a case, the sensing voltage at the v s pin of the irs20124 is clamped by the body diode. this means that the effective r ds(on) is now much lower than expected from r ds(on) of the mosfet, and the v s node my not able to reach the threshold to turn the oc output on before the mosfet fails. therefore, the region where body diode clamping takes a place should be avoided when setting v soc- . for further application information for gate driver ic please refer to an-978 and dt98-2a. for fur- ther application information for class d applica- tion, please refer to an-1070 and an-1071. body diode in mosfet clamps vs voltage v s - com i d body diode clamp ocset2 should be set in this region } 0
www.irf.com 25 irs20124s (pbf) 01-6019 01-3063 00 (ms-012ab) 14 lead soic (narrow body) case outline
www.irf.com 26 irs20124s (pbf) carrier tape dimension for 14soicn code min max min max a 7.90 8.10 0.311 0.318 b 3 .9 0 4.1 0 0.15 3 0 .1 61 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 6.40 6.60 0.252 0.260 f 9.40 9.60 0.370 0.378 g 1 .5 0 n/a 0.05 9 n/a h 1.50 1.60 0.059 0.062 m etr ic im p erial reel dimensions for 14soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 m etr ic im p erial e f a c d g a b h n ot e : co ntrolling d imension in mm load ed ta pe feed direction a h f e g d b c tape & reel 14-lead soic
www.irf.com 27 irs20124s (pbf) so-14 package is msl2 qualified. this product has been designed and qualified for the industrial level. qualification standards can be found at ir's web site http://www.irf.com world headquarters: 233 kansas st., el segundo, california 90245 tel:(310) 252-7105 data and specifications subject to change without notice. 12/4/2006 14-lead soic irs20124spbf 14-lead soic tape & reel IRS20124STRPBF leadfree part marking information lead free released non-lead free released part number date code irsxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code order information

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